Texas Instruments /MSP432E411Y /LCD0 /DMACTL

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Interpret as DMACTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCD_DMACTL_FMODE)LCD_DMACTL_FMODE 0 (LCD_DMACTL_BIGDEND)LCD_DMACTL_BIGDEND 0 (LCD_DMACTL_BYTESWAP)LCD_DMACTL_BYTESWAP 0LCD_DMACTL_BURSTSZ 0 (LCD_DMACTL_FIFORDY_8)LCD_DMACTL_FIFORDY

LCD_DMACTL_FIFORDY=LCD_DMACTL_FIFORDY_8

Description

LCD DMA Control

Fields

LCD_DMACTL_FMODE

Frame Mode

LCD_DMACTL_BIGDEND

Big Endian Enable

LCD_DMACTL_BYTESWAP

This bit controls the bytelane ordering of the data on the output of the DMA module

LCD_DMACTL_BURSTSZ

Burst Size setting for DMA transfers (all DMA transfers are 32 bits wide):

2 (LCD_DMACTL_BURSTSZ_4): burst size of 4

3 (LCD_DMACTL_BURSTSZ_8): burst size of 8

4 (LCD_DMACTL_BURSTSZ_16): burst size of 16

LCD_DMACTL_FIFORDY

DMA FIFO threshold

0 (LCD_DMACTL_FIFORDY_8): 8 words

1 (LCD_DMACTL_FIFORDY_16): 16 words

2 (LCD_DMACTL_FIFORDY_32): 32 words

3 (LCD_DMACTL_FIFORDY_64): 64 words

4 (LCD_DMACTL_FIFORDY_128): 128 words

5 (LCD_DMACTL_FIFORDY_256): 256 words

6 (LCD_DMACTL_FIFORDY_512): 512 words

Links

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